Low power built-in self-test schemes for array and booth multipliers

Recent trends in IC technology have given rise to a new requirement, that o f low power dissipation during testing, that Built-In Self-Test (BIST) stru ctures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modi fied Booth multipliers, in this paper we propose new power-efficient BIST s tructures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs , (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be redu ced from 29.3% to 54.9%, while the average power per test vector applied ca n be reduced from 5.8% to 36.5% and the peak power dissipation can be reduc ed from 15.5% to 50.2% depending on the implementation of the basic cells a nd the size of the multiplier. The test application time is also significan tly reduced, while the introduced BIST schemes implementation area is small .