Simultaneous switching noise minimization technique using dual layer powerline mutual inductors

A novel technique for minimization of simultaneous switching noise is prese nted. Dual Layer Power Line (DLPL) structure is newly proposed for a possib le silicon realization of a mutual inductor, with which an instant large cu rrent in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance betw een two power layers enables us to significantly minimize the switching noi se. SPICE simulations show that with a mutual coupling coefficient higher t han 0.8, the switching noise reduces by 63% compared to the previously repo rted solutions. This DLPL technique can also be applied to PCB artworks.