Asynchronous cross-pipelined multiplier

Citation
J. Butas et al., Asynchronous cross-pipelined multiplier, IEEE J SOLI, 36(8), 2001, pp. 1272-1275
Citations number
19
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
8
Year of publication
2001
Pages
1272 - 1275
Database
ISI
SICI code
0018-9200(200108)36:8<1272:ACM>2.0.ZU;2-E
Abstract
In this paper, a design of a 16-bit asynchronous multiplier is presented. T he multiplier core consists of small basic blocks. Each block includes hand shake and computation logic and communicates with four neighbor cells in as ynchronous handshake fashion using four-phase protocol. The computation log ic is implemented in dual-rail coded domino logic. The input and output sig nals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four- phase signaling. The design speed is self-adjusting to the technology param eters and supply voltage variations. The multiplier has low latency and ach ieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6- mum CMOS process and has a core size of 4.3 x 2.1 mm.