Asynchronous cross-pipelined multiplier

In this paper, a design of a 16-bit asynchronous multiplier is presented. T he multiplier core consists of small basic blocks. Each block includes hand shake and computation logic and communicates with four neighbor cells in as ynchronous handshake fashion using four-phase protocol. The computation log ic is implemented in dual-rail coded domino logic. The input and output sig nals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four- phase signaling. The design speed is self-adjusting to the technology param eters and supply voltage variations. The multiplier has low latency and ach ieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6- mum CMOS process and has a core size of 4.3 x 2.1 mm.