A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-in terpolation technique is fabricated using 0.35-mum CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most s ignificant bit (MSB) of the accumulator in this DDS. To improve the spectra l performance, a method of spurious signal reduction that uses offset curre nt sources (OCSs) is newly adopted in the delay generator. Test results con firm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic r ange (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption o f the complete DDS is 39.2 mW at a 100-MHz clock rate.