Fast modeling of core switching noise on distributed LRC power grid in ULSI circuits

As technology scales, power supply noise caused by core logic switching bec omes critical. Shorter signal rise edge, high integration density, and nece ssity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with mi llions of switching devices. In this paper, we propose a sophisticated powe r grid model consisting of distributed LRC elements excited by constant vol tage sources and switching capacitors. Based on this, fast equations for co re switching noise estimations were formulated. Full-chip noise distributio n on the power grid with any topology was efficiently and accurately comput ed. SPICE simulations confirmed its efficiency and accuracy. Experimental r esults obtained on our benchmark circuits revealed that the proposed techni que speeded up simulations by several orders of magnitude compared with SPI CE, whereas typical relative error was between 0 +/- 5 %. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power no ise. Meanwhile, locations of hot spots in the power network are precisely i dentified. The model is suitable for full-chip rapid simulations for on-chi p power distribution design in advanced ultra large scale integration (ULSI ) circuits, particularly for early stage analysis, in which global and loca l optimization such as topology selection, power bus sizing, and on-chip de coupling capacitor placement can be easily conducted.