Understanding the evolution of trench profiles in the via-first dual damascene integration scheme

The introduction of copper interconnects into integrated circuits has incre ased the use of dual damascene dielectric etch applications because copper films are difficult to plasma etch. Fencing and faceting around the via hol e during the trench etch of the via-first dual damascene integration scheme are particularly detrimental and can lead to problems during copper metall ization and ultimately to device failure. Therefore, it is imperative that the evolution of these features be understood so that they can be avoided. In this article we will begin with an over-view of the via-first dual damas cene integration scheme. Experimental results will then be presented that i ndicate the evolution of these features is heavily dependent upon the exist ing via profile and whether bottom antireflection coating and/or photoresis t is in the via hole prior to starting the trench etch. An empirical model for fence formation was then confirmed by a simple profile simulator writte n in Visual Basic. Finally, several options for avoiding the evolution of f encing and faceting during the trench etch will be proposed. (C) 2001 Ameri can Vacuum Society.