Hierarchical fault diagnosis of analog integrated circuits

This paper introduces a hierarchical-fault-diagnosis algorithm as an aid to testing analog and mixed signal circuits. The diagnosis approach is based on that introduced by Wey and others and makes use of the self-test algorit h, and the component-connection model. The main extension to these techniqu es is the use of a hierarchical approach whereby blocks of circuitry are gr ouped together leading to a reduction in matrix size, so making even large scale circuits diagnosable. Other improvements from this approach include a novel test-point selection procedure and the fact that hard faults can als o be diagnosed, provided they lie completely within a hierarchical block. The overall algorithm is described and the results from example circuits sh ow good functionality of the diagnosis algorithm. Fault masking and sensiti vity to the simulation/measurement resolution of test point values are exam ined and are highlighted as future activities to further improve the approa ch.