The effects of inductance on repeater insertion in RLC trees is the focus o
f this paper. An algorithm is introduced to insert and size repeaters withi
n an RLC tree to optimize a variety of possible cost functions such as mini
mizing the maximum path delay, the skew between branches, or a combination
of area, power, and delay. The algorithm has a complexity proportional to t
he square of the number of possible repeater positions and determines a rep
eater solution that is close to the global minimum. The repeater insertion
algorithm is used to insert repeaters within several copper-based interconn
ect trees to minimize the maximum path delay based on both an RC model and
an RLC model. The two buffering solutions are compared using the AS/X dynam
ic circuit simulator. It is shown that as inductance effects increase, the
area and power consumed by the inserted repeaters to minimize the path dela
ys of an RLC tree decreases. By including inductance in the repeater insert
ion methodology, the interconnect is modeled more accurately as compared to
an RC model, permitting average savings in area, power, and delay of 40.8%
, 15.6%, and 6.7%, respectively, for a variety of copper-based interconnect
trees from a 0.25-mum CMOS technology. The average savings in area, power,
and delay increases to 62.2%, 57.2%, and 9.4%, respectively, when using fi
ve times faster devices with the same interconnect trees.