A unified systolic array design for kernel functions of video compression

In video compression, some kernel functions such as block matching, discret e wavelet transform, vector quantization, etc., are of prime essential, but with a large amount of computation. Recently, many systolic array architec tures have been designated for performing each of those functions in real t ime. In fact, many kernel functions contain the similar computational proce dure. If we dissect these functions into the basic matrix-vector product fo rms, a unified design for them becomes feasible. In this brief, by carefull y extracting the common computation component, a unified one-dimensional sy stolic array design that can perform at least the above three functions is presented. In this design, the input data is serial-in to save the amount o f pins required, and the data flow are carefully arranged to simplify the i nterconnection between computation components. When 64 registers are in the on-chip memory, our design can perform three typical functions: 1) the ful l-search block matching with block size 16 X 16 and the search range (-8, 7 ); 2) the 2-D Harr transform with block size 8 X 8; and 3) the vector quant ization with input vector size 4 X 4 and codebook size 256. Since the unifi ed architecture reduces hardware costs, and has a regular hardware structur e, it is suited for VLSI implementation for video/image compression applica tions that require all the functions.