Chip-delay locked matched filter for DS-CDMA systems using long sequence spreading

Authors
Citation
Yc. Yoon et H. Leib, Chip-delay locked matched filter for DS-CDMA systems using long sequence spreading, IEEE COMMUN, 49(8), 2001, pp. 1468-1478
Citations number
35
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
IEEE TRANSACTIONS ON COMMUNICATIONS
ISSN journal
00906778 → ACNP
Volume
49
Issue
8
Year of publication
2001
Pages
1468 - 1478
Database
ISI
SICI code
0090-6778(200108)49:8<1468:CLMFFD>2.0.ZU;2-C
Abstract
This paper considers an improved single-user detection technique for asynch ronous direct-sequence code-division multiple-access (DS-CDMA) systems usin g long sequence spreading (random-CDMA). Most of the known detection scheme s for DS-CDMA suffer from either poor performance under power-imbalance (ne ar-far like) conditions, excessive complexity, or incompatibility with syst ems employing long sequence spreading. To address these problems, this pape r considers a signal-to-noise ratio maximizing linear time-invariant filter for one-shot bit symbol detection exploiting some information about the in terferers. This filter, referred to as the chip-delay locked matched filter (CLMF), exploits the cyclostationarity in multiple-access interference, an d it can offer good near-far resistance while remaining suitable for system s with long sequence spreading. The CLMF requires knowledge of interferers chip delays and signal powers; however, knowledge of their pseudonoise sequ ences is unnecessary. This paper also demonstrates the improvement in perfo rmances offered by the CLMF over other single-user receivers such as the co nventional matched filter and noise-whitening matched filter. Performance i s evaluated in terms of probability of outage for single-rate and dual-rate DS-CDMA systems using bandwidth-efficient chip pulses, over a single-path additive white Gaussian noise channel. Errors in the interferers chip delay estimates degrade the CLMF performance. However, if the root-mean-square v alue of these errors is less than 5% of the chip interval, then this degrad ation is small.