Sub-100 nm CMOS circuit performance with high-K gate dielectrics

In this paper we look at the effect of fringing fields on the circuit perfo rmance by use of high permittivity (K) gate dielectrics in 70 nm CMOS techn ologies, from Monte-Carlo and mixed-mode simulations. Our results clearly s how a decrease in the external fringing capacitance and an increase in the internal fringing capacitance, when the conventional SiO2 is replaced by hi gh-K gate dielectrics. It also indicates an optimum K value for a given tec hnology generation in terms of circuit and device short-channel performance . (C) 2001 Elsevier Science Ltd. All rights reserved.