High-bandwidth x86 instruction fetching based on instruction pointer table

Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a c ycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing and processing the pre-decoded information in the c ache. In the paper, the authors propose to use an Instruction Identifier to predict instruction length and store the instruction pointers as superscal ar instruction group indicators. With this method, the difficulty of achiev ing a high instruction fetch degree (>3) can be overcome. Simulation result s suggest that the Instruction Identifier with a 64-entry table is a good p erformance/cost choice. In the meantime, as the table size decreases, the p rediction scheme becomes increasingly important. Moreover, simulation and c ircuit synthesis show that this design is feasible for high clock rate desi gn.