Multiple-level logic simulation algorithm

An algorithm for the simulation of gate-level logic is presented. Multiple logic levels are used to describe the state of each node. Each state corres ponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the int erface between a digital and an analogue simulator. A Boolean equation solv er is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops, and to determine whethe r the network has no, one or multiple solutions. In the latter case, the so lver can identify the nodes whose values are undetermined, thus avoiding th e need to initialize-all nodes in the network to an unknown state 'X'. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstra ted by simulations of a number of benchmark circuits.