Electrical transport in nano-scale silicon devices

This paper reviews our experimental results for electrical transport proper ties of nano-scale silicon metal-oxide-semiconductor field-effect transisto rs (MOSFETs). We used very small devices produced using 10-nm-scale lithogr aphic techniques: electrically variable shallow junction MOSFETs (EJ-MOSFET s) and lateral hot-electron transistors (LHETs). With LHETs we succeeded in directly detecting the hot-electron current and estimated the characterist ic length to be around 25 nm. We also investigated the energy relaxation me chanism by performing measurements at various applied voltages and temperat ures. Furthermore, we clearly observed the tunneling current between the so urce and drain (source-drain tunneling) in an 8nm-gate-length EJ-MOSFET. Ba sed on these experimental results, we predict the limitation of MOSFET mini aturization to be around 5 nm in the source-drain tunneling scheme.