Strained-Si-on-insulator (strained-SOI) MOSFETs - Concept, structures and device characteristics

An effective way to realize scaled CMOS with both requirements of high curr ent drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strai ned-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advant ages of strained-SOI MOSFETs are presented. It is demonstrated that straine d-SOI MOSFETs are successfully fabricated by combining SIMOX technology wit h re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 a nd 1.3 times higher than the universal one, respectively. Furthermore, it i s also shown that ultra-thin Site-on-Insulator (SGOI) virtual substrates wi th higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure wit h lower Ge content.