Silicon planar Esaki diode operating at room temperature

Negative differential conductance based on lateral interband tunnel effect is demonstrated in a planar degenerate p(+)-n(+) diode (Esaki tunnel diode) . The device is fabricated with the current silicon ultralarge scale integr ation (Si ULSI) process, paying attention to the processing damage so as to reduce an excess tunnel current that flows over some intermediate states i n the tunnel junction. I-V characteristics at a low temperature clearly sho w an intrinsic electron transport, indicating phonon-assisted tunneling in Si as in the case of the previous Esaki diodes fabricated by the alloying m ethod. In addition, a simple circuit function of bistable operation is demo nstrated by connecting the planar Esaki diode with conventional Si metaloxi de-semiconductor field effect transistors (MOSFETs). The planar Esaki diode will be a promising device element in the functional library for enhancing the total system performance for the coming system-on-a-chip (SoC) era.