Resolution enhancement techniques for high-speed multi-stage pipelined ADC's based on a multi-bit multiplying DAC

This paper proposes resolution enhancement techniques for high-speed multi- stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/s tage multiplying digital-to-analog converter. The proposed techniques incre ase ADC resolution and simultaneously minimize chip area, power dissipation . and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated . The resolution of the proposed ADC can be extended furthermore by combini ng a conventional commutated feedback-capacitor switching scheme with the d igital-domain self calibration.