Code optimization technique for indirect addressing DSPs with consideration in local computational order and memory allocation

Digital signal processors (DSPs) usually employ indirect addressing using a ddress registers (ARs) to indicate their memory addresses. which often intr oduces overhead codes in AR updates for next memory accesses. Reduction of. ,uch overhead code is one of the important issued in automatic generation o f highly-efficient DSP codes. In this paper, a new automatic address alloca tion method interpolated with computational order rearrangement at local co mmutative parts is proposed. The method formulates a given memory access se quence by a graph representation, where several strategies to handle freedo m in memory access orders at the computational commutative parts are introd uced and examined. A compiler scheme is also extended such that computation al order at the commutative parts is rearranged according to the derived me mory allocation. The proposed methods are applied to an existing DSP compil er for mu PD77230(NEC), and codes generated for several examples are compar ed with memory allocations by the conventional methods.