Design of FIR digital filters with CSD coefficients having power-of-two DCgain and their FPGA implementation for minimum critical path

For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose po wer-of-two DC gain is proposed. Output signal level call easily be compensa ted to that of input so that cascading many stages do not cause any gain er rors, which are harmful in, for example, high precision measurement systems . The design is formulated as an optimization problem with magnitude respon se constraints. The integer linear programming modified for CSD codes is so lved by the branch and bound method, The design example shows the effective ness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field progra mmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the d ie area.