Latchup characterization of 0.18-micron STI cobalt silicided test structures

The effects of varying both the Shallow Trench Isolation's (STI) dimension and geometrical spacings on latchup behavior for 0.18-mum cobalt silicided CMOS test structures were investigated. The as-developed characterization t echniques and models aid in the optimization of device layout. The test dat a extracted for both the parasitic current gains and parasitic resistances over a range of layout dimensions were analyzed and modeled. The influence of biasing voltages on latchup reliability was also studied. (C) 2001 Elsev ier Science Ltd. All rights reserved.