On-chip ESD protection design for integrated circuits: an overview for IC designers

This tutorial paper reviews the state of knowledge of on-chip ESD (electros tatic discharging) protection circuit design for integrated circuits. The d iscussion covers critical issues in ESD protection design, i.e. ESD test mo dels, ESD failure mechanisms, ESD protection structures, ESD device modelin g, ESD simulation, ESD layout issues, and ESD-to-circuit interactions, etc. This review serves to provide practical IC designers with a thorough and h eady reference in dealing with complex ESD protection design for integrated circuits. (C) 2001 Published by Elsevier Science Ltd.