CalmRISC (TM): a low power microcontroller with efficient coprocessor interface

This paper presents the low power architecture of CalmRISC, a low power 8-b it microcontroller consuming only 0.1 mW per MIPS at 3.0 V, and its efficie nt coprocessor interface. The architectural consideration of CalmRISC for l ow power consumption is presented. Some low power circuit design schemes as well as an efficient coprocessor interface scheme in CalmRISC are proposed and discussed. Finally, the implementation results of CalmRISC and MAC816, one of its DSP coprocessors, as well as C-compiler issues are presented. ( C) 2001 Elsevier Science B.V. All rights reserved.