Interfacial charge trapping in extrinsic Y2O3/SiO2 bilayer gate dielectricbased MIS devices on Si(100)

Metal-insulator-semiconductor (MIS) structures based on an extrinsic Y2O3 d ielectric film on Si show high leakage currents due to roughness-related hi ghly localized fields. Oxygen annealing increases the dielectric constant a nd strength and reduces leakage currents by transforming Y2O3 (film)/Si(100 ) into a bilayer Y2O3 (film)/SiO2/Si(100) dielectric structure. Evolution o f interfacial SiO2 causes generation of mid-gap interface states at E-v + 0 .23 eV and E-v + 0.43 eV, which act as electron traps and are responsible f or hysteresis effects in capacitance-voltage (C-V) and current-voltage (I-V ) behaviour in the accumulation-inversion modes. The electron trapping redu ces the cathodic field and causes lowering of the current and the shift in current to higher fields after successive ramps. The charge trapping effect s cause varied and unstable C-V and I-V behaviour of MIS structures based o n a Y2O3/SiO2 bilayer gate dielectric. Its origin has been attributed to mi crostructure and defect state modification at the Y2O3 film-Si interface. T his limits its application in high-density dynamic random access memory and ultra-large-scale integration devices.