Von Neumann hybrid cellular automata for generating deterministic test sequences

We propose an on-chip test pattern generator that uses an one-dimensional c ellular automaton (CA) to generate either a precomputed sequence of test pa tterns or pairs of test patterns for path delay faults. To our knowledge, t his is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) u sing a finite number of CA cells. Given a pair of columns (C-u, C-v) of the test matrix, the proposed method uses alternative "link procedures" P-j th at compute the number of extra CA cells to enable the generation of (C-u, C -v) by the CA. A systematic approach uses the link procedures to minimize t he total number of needed CA cells. The performance of the scheme depends o n an appropriate choice of link procedures P-j.