To obtain a high resolution CMOS current-steering digital-to-analog convert
er, the matching behavior of the current source transistors is one of the k
ey issues in the design. At this moment, these matching properties are take
n into account by the use of time consuming and CPU intensive Monte Carlo s
imulations. In this paper, a formula is derived that describes accurately t
he impact of the mismatch on the INL (integral non-linearity) yield of curr
ent-steering D/A converters without any loss of design time.