CLOCK SKEW MINIMIZATION DURING FPGA PLACEMENT

Unlike traditional ASIC technologies, the geometric structures of cloc k trees in a field-programmable gate array (FPGA) are usually fixed an d cannot be changed for different circuit designs, Furthermore, the cl ock pins are connected to the clock trees via programmable switches. A s a result, the load capacitances of a clock tree may be changed, depe nding on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock skew by carefully distributing the l oad capacitances or, equivalently, the logic modules used for the circ uit design implementation. In this paper we present an algorithm for s electing logic modules used for circuit placement such that the clock skew is minimized, The algorithm can be applied to a variety of clock tree architectures, Including those used in the major commercial FPGA' s. The algorithm can also be extended to handle buffered clock trees a nd multiple clock trees, Experimental results show that the algorithm can reduce clock skews significantly as compared with the traditional placement algorithms which do not consider clock skew minimization.