Mechanisms of the chemical mechanical polishing (CMP) process in integrated circuit fabrication

A contact mechanics model that describes the polishing mechanisms of copper -patterned silicon wafers in the fabrication of ultra-large-scale integrate d (ULSI) circuits is presented. The model explains the die-scale variation of material removal rates due to pattern geometry, and predicts results tha t are in agreement with experimental observations. When the width of the co pper interconnect is less than 0.5 mum, dishing of interconnects is less th an 20 nm and thus does not contribute much to surface nonuniformity. Howeve r, because the overpolishing rate varies with the copper area fraction, it may contribute to die-scale nonuniformity.