ASMD with duty cycle correction scheme for high-speed DRAM

Authors
Jang, SJ Jun, YH Lee, JG Kong, BS
Citation
Sj. Jang et al., ASMD with duty cycle correction scheme for high-speed DRAM, ELECTR LETT, 37(16), 2001, pp. 1004-1006
Citations number
3
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
37
Issue
16
Year of publication
2001
Pages
1004 - 1006
Database
ISI
SICI code
0013-5194(20010802)37:16<1004:AWDCCS>2.0.ZU;2-B
Abstract
An analogue synchronous mirror delay with duty cycle correction scheme (ASM DCC), to improve the data transmission performance between DRAM and system. is proposed. The ASMDCC achieves duty cycle correction and clock synchroni sation at once within two clock cycles, by using a half value current sourc e. The simulation results show the duty cycle of the internal clock is stab ilised with less than +/- 100ps deviation from 50% for the wide duty cycle range.