Offset in CMOS magnetotransistors - Part I: Analysis of causes

Fabrication imperfections cause offset in CMOS magnetotransistors (MTs). In this paper, MT offset is experimentally characterized and its causes are a nalyzed for two different commercial CMOS processes. For the MT structures chosen as references, the average absolute value of the offset in terms of a relative imbalance of two collector currents is up to 2.7%. The mean offs et temperature drift between -40 degreesC and +140 degreesC is 0.25%. The o ffset exhibits a high degree of variation on a very small spatial scale. Ad ditionally, variations on a large scale over the wafer are observed and, in some cases, systematic influences. The actual offset contributions of the various identified possible sources are investigated. Misalignment of the m etal contact mask occurring during photolithography dominates large scale o ffset variations and can also have a systematic component. Another systemat ic influence arises from nonorthogonal dopant implantation. Doping inhomoge neities are a dominating contribution, to local variations as indirect evid ence suggests. Further, mismatch in emitter-collector spacing is critical. Suppressed sidewall injection magnetotransistors (SSIMTs) showing an enhanc ed sensitivity exhibit a quadrupling of the offset, which comes from a misa lignment of the emitter guard ring. The obtained results are the basis for dedicated offset reduction in MTs as well as the development of MT-like tes t structures for processing tolerances.