Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into a n elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capac itance as well as the junction leakage was significantly reduced for an NMO SFET while maintaining its good short channel characteristics. These succes sful results are attributed to the modification of the boron impurity profi le in the deep S/D regions. The capacitance reduction rate, furthermore, wa s more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be req uired to suppress the short channel effect.