Optimized circuit architecture for VLSI ROTOR processors

The principle of operation of rotational trapezoidal readout (ROTOR), a nov el processor of nuclear signals, has been recently demonstrated. Neverthele ss the prototypes realized so far are affected by limiting factors that do not permit to fully exploit the potentialities of the ROTOR principle. For example, currently the weighting function is trapezoidal, which is not opti mal for low-rate operation and/or when the 1/f noise of the preamplifier is not negligible. Furthermore, a very precise timing must be supplied for pr oper operation. In this paper, we suggest that these limitations can be ove rcome by: 1) shrinking the analog pulses provided by the preamplifier; 2) s upplying them to the reference input of a digital-to-analog converter (DAC) used as a multiplier, whose digital-input tracks the wanted weighting func tion; and 3) integrating the signal at the DAC output. In this way, on the one hand the weighting function may be shaped so as to match the optimal pr ofile, on the other hand precision is no longer required in the gating inte rvals, where the flat top and the shoulders of the weighting function lay. Eventually, the proposed solution is shown to be less sensitive to the para meter-matching accurateness of the used technology.