A pipelined architecture for the multidimensional DFT

Citation
Sw. Yu et Ee. Swartzlander, A pipelined architecture for the multidimensional DFT, IEEE SIGNAL, 49(9), 2001, pp. 2096-2102
Citations number
16
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON SIGNAL PROCESSING
ISSN journal
1053587X → ACNP
Volume
49
Issue
9
Year of publication
2001
Pages
2096 - 2102
Database
ISI
SICI code
1053-587X(200109)49:9<2096:APAFTM>2.0.ZU;2-3
Abstract
This paper presents an efficient pipelined architecture for the N-m-point m -dimensional discrete Fourier transform (DFT). By using a two-level index m apping scheme that is different from the conventional decimation-in-time (D IT) or decimation-infrequency (DIF) algorithms, the conventional pipelined architecture for the one-dimensional (1-D) fast Fourier transform (FFT) can be efficiently used for the computation of higher dimensional DFTs. Compar ed with systolic architectures, the proposed scheme is area-efficient since the computational elements (CEs) use the minimum number of multipliers, an d the number of CEs increases only linearly with respect to the dimension m . It can be easily extended to the N-m-point m-dimensional DFT with large m and/or N, and it is more flexible since the throughput can be easily varie d to accommodate various area/throughput requirements.