Ultrashallow junction formation for sub-100 nm complementary metal-oxide-semiconductor field-effect transistor by controlling transient enhanced diffusion

The annealing process of implantation damage that induces transient enhance d diffusion during a subsequent thermal process such as low-pressure chemic al vapor deposition (LPCVD) is optimized from the viewpoint of the process integration of an 80 run physical gate length complementary metal-oxide-sem iconductor field-effect transistor (CMOSFET) device. For nMOSFETs, a temper ature as high as 960 degreesC is necessary to prevent transient enhanced di ffusion. In contrast, for pMOSFETs, higher temperature annealing promotes t hermal diffusion instead of preventing enhanced diffusion. It is found that a separate annealing process sequence is required. In utilizing preamorphi zation implantation prior to boron implantation, however, higher temperatur e annealing is effective for forming an ultrashallow junction. Consequently , the annealing processes can be performed simultaneously.