Analysis and improvement of retention time of memorized state of metal-ferroelectric-insulator-semiconductor structure for ferroelectric gate FET memory
M. Takahashi et al., Analysis and improvement of retention time of memorized state of metal-ferroelectric-insulator-semiconductor structure for ferroelectric gate FET memory, JPN J A P 1, 40(4B), 2001, pp. 2923-2927
Retention characteristics of metal-ferroelectric-insulator-semiconductor (M
FIS) structures have been studied theoretically by considering effects of c
harge injections derived from the difference between leakage current densit
ies in the ferroelectric and insulator layers. The calculated curves for ti
me-dependent capacitance have shown good agreements with experimental resul
ts. The numerical results for the MFIS structure have indicated that excess
current over a certain value through the ferroelectric and the insulator l
ayers causes the retention time to rapidly degrade. An idea of inserting an
insulator film between the metal and the ferroelectric layers in an MFIS h
as also been examined in order to cut down the currents through the ferroel
ectric layer. The calculations based on our model have found this metal-ins
ulator-ferroelectric-insulator-semiconductor (M-I-FIS) structure to exhibit
much longer retention time than the conventional MFIS.