Fabrication technologies for Double-SiO2-barrier metal-oxide-semiconductortransistor with a poly-Si dot

A double-tunnel-barrier (1.7-nm-thick SiO2) metal-oxide-semiconductor (MOS) transistor with a poly-Si dot was proposed as a single-electron transistor (SET). The simulation results indicated that room-temperature operation of the SET is possible when the poly-Si dot size is in the order of similar t o 10nm. Technologies for the fabrication of the MOS transistor were develop ed. We have evalulated plasma-induced damage at the sidewall of the Si tren ch in which a poly-Si dot is embedded. It was found that a sacrificial oxid ation of 20 nm is necessary to remove the plasma-induced damage. In order t o assure complete electrical isolation of the source and the drain by the t rench, simulation of the impurity (arsenic, phosphorous and boron) profiles for the MOS transistor with a trench (200 nm length x 200 nm depth) were c arried out. Test MOS transistors with a poly-Si dot (200 nm length x 200 nm height x 50-100 nm width) were fabricated. However, the device showed an a bnormally large current which may be ascribed to the residual poly-Si in th e trench outside of the dot region.