Design considerations for low-power single-electron transistor logic circuits

We have investigated design considerations for low-power single-electron tr ansistor (SET) logic circuits. Supply-voltage scaling is introduced as a me thod for reducing the power consumption of SET circuits. A detailed analysi s of the effects of supply-voltage scaling is given on the basis of the beh avior of a complementary capacitively coupled SET inverter circuit. It has been shown that the hysteresis caused by the supply-voltage-dependent thres hold voltage of a SET quickly disappears as the temperature rises, and does not ruin the desired inverting operation at a practical operation temperat ure. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. From the results of power-delay product and delay time. it has been shown that the supply-v oltage scaling should be carried out within 20% of maximum supply-voltage t o maintain overall circuit performance.