BUFFERED CLOCK TREE SYNTHESIS WITH NONZERO CLOCK SKEW SCHEDULING FOR INCREASED TOLERANCE TO PROCESS PARAMETER VARIATIONS

An integrated top-down design system is presented in this paper for sy nthesizing clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circui t, and used to determine a non-zero clock skew schedule which reduces the clock period as compared to zero skew-based approaches. Concurrent ly, the permissible range of clock skew for each local data path is ca lculated to determine the maximum allowed variation of the scheduled c lock skew such that no synchronization failures occur. The choice of c lock skew values considers several design objectives, such as minimizi ng the effects of process parameter variations, imposing a zero clock skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value. The clock skew schedule and the worst case variation of the primary proce ss parameters are used to determine the hierarchical topology of the c lock distribution network, defining the number of levels and branches of the clock tree and the delay associated with each branch. The delay of each branch of the clock tree is physically implemented with distr ibuted buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and th e characteristics of the clock tree interconnect. A bottom-up approach for calculating the worst case variation of the clock skew due to pro cess parameter variations is integrated with the top-down synthesis sy stem. Thus, the local clock skews and a clock distribution network are obtained which are more tolerant to process parameter variations. Thi s methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock freq uency of up to 43% as compared with zero clock skew implementations ar e shown. Furthermore, examples of clock distribution networks that exp loit intentional localized clock skew are presented which are tolerant to process parameter variations with worst case clock skew Variations of up to 30%.