USEFUL-SKEW CLOCK ROUTING WITH GATE SIZING FOR LOW-POWER DESIGN

This paper presents a new problem formulation and algorithm of clock r outing combined with gate sizing for minimizing total logic and clock power. Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that only positive skew should be minimized while negative skew is use ful in that it allows a timing budget larger than the clock period for gate sizing. We construct an useful-skew tree (UST) such that the tot al clock and logic power (measured as a cost function) is minimized. G iven a required clock period and feasible gate sizes, a set of negativ e and positive skew bounds are generated. The allowable skews within t hese bounds and feasible gate sizes together form the feasible solutio n space of our problem. Inspired by the Deferred-Merge Embedding (DME) approach, we devise a merging segment perturbation procedure to explo re various tree configurations which result in correct clock operation under the required period. Because of the large number of feasible co nfigurations, we adopt a simulated annealing approach to avoid being t rapped in a local optimal configuration. This is complemented by a bi- partitioning heuristic to generate an appropriate connection topology to take advantage of useful skews. Experimental results of our method have shown 12% to 20% total power reduction over previous methods of c lock routing with zero-skew or a single fixed skew bound and separatel y sizing logic gates. This is achieved at no sacrifice of clock freque ncy.