PRACTICAL BOUNDED-SKEW CLOCK ROUTING

In Clock routing research, such practical considerations as hierarchic al buffering, rise-time and overshoot constraints, obstacle- and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores dire ctions in which traditional formulations can be extended so that the r esulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing f or varying layer parasitics with non-zero via parasitics; (ii) obstacl e-avoidance clock routing; and (iii) hierarchical buffered tree synthe sis. We develop new theoretical analyses and heuristics, and present e xperimental results that validate our new approaches.