TIMING OF MULTIGIGAHERTZ RAPID SINGLE FLUX QUANTUM DIGITAL CIRCUITS

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative t o advanced semiconductor technologies for large scale ultra-high speed , very low power digital applications. Timing of RSFQ circuits at freq uencies of tens to hundreds of gigahertz is a challenging and still un resolved problem. Despite the many fundamental differences between RSF Q and semiconductor logic at the device and at the circuit level, timi ng of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits. Th is paper is intended as a comprehensive review of RSFQ timing, from th e viewpoint of the principles, concepts, and language developed for se miconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design me thodologies as well as those developed specifically for RSFQ logic. Th e primary features of these synchronization schemes, including timing equations, are presented and compared. In many circuit topologies of c urrent medium to large scale RSFQ circuits, single-phase synchronous c locking outperforms asynchronous schemes in speed, device/area overhea d, and simplicity of the design procedure. Synchronous clacking of RSF Q circuits at multigigahertz frequencies requires the application of n on-standard design techniques such as pipelined clocking and intention al non-zero clock skew. Even with these techniques, there exist diffic ulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchroniza tion techniques, including but not limited to asynchronous timing, sho uld be considered for certain circuit topologies. A synchronous two-ph ase clocking scheme for RSFQ circuits of arbitrary complexity is intro duced, which for critical circuit topologies offers advantages over pr evious synchronous and asynchronous schemes.