How we implemented block turbo codes?

This paper presents a block turbo decoding algorithm, from its theory to it s implementation in a programmable circuit. In this study, we discuss the t wo prototypes realized. It will be possible to compare the complexity of th e core of the process, which is the elementary decoder, thanks to the choic e of essential parameters. One prototype is more dedicated to high data rat es, the other one being implemented on only one FPGA which means a gain in terms of area. First, we briefly focus on the description of the siso (Soft-In Soft-out) a lgorithm used to implement the turbo decoder Then, we explain the essential choices in order to adapt the algorithm for an ASIC implementation, which leads to a compromise between area and binary error rate. Finally, we prese nt the two prototypes implemented and their experimental results.