This paper presents a synthesis algorithm toy digital signal processing (DS
P) processor design that uses data pipelining to achieve high throughput an
d low cost. The hardware resources, which are composed of function units, r
egister units, bus units, and memory units in an executing model, are descr
ibed. Under the constraints in the resource library, the DSP data is read i
n as a control data flow graph. The resources selection, mapping, and shari
ng are conducted based on our algorithm. The experimental and comparative r
esults are discussed.