Wiring of bumpless, three-dimensional integrated Si wafers block using through-hole interconnections

Authors
Citation
A. Satoh, Wiring of bumpless, three-dimensional integrated Si wafers block using through-hole interconnections, JPN J A P 1, 40(8), 2001, pp. 4774-4780
Citations number
8
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science
Volume
40
Issue
8
Year of publication
2001
Pages
4774 - 4780
Database
ISI
SICI code
Abstract
Through-holes having an aspect ratio of 52.5 were formed with a hole densit y of 11.6 holes/mm(2) on N-type Si wafers (Miller index: 100), using the op tical excitation electropolishing method (OEEM). These Si wafers were bonde d together in the three-dimensional direction by water glass bonding to for m a five-laver integrated block. All wiring of this integrated block was pe rformed in one operation by refilling the through-holes of the block with m etal (indium) from the holes in its bottom surface by the closed type molte n metal suction method. At the same time, the wiring trenches which require low resistance were also fi I led with metal. This is a new method of wiri ng the wafer-level. three-dimensional integrated block without the need for inner bumps. In addition. we have found a method of controlling the contac t angle of metal with respect to SiO2 by the field effect utilizing a metal oxide semiconductor (MOS) structure to prevent the metal put in deep capil laries from dropping due to its own weight. This technology is a break-thro ugh in packaging wafer-level, ultra-high-density three-dimensional integrat ed blocks which will be needed in the first half of the 21st century.