A modified capacitance-voltage method used for L-eff extraction and process monitoring in advanced 0.15 mu m complementary metal-oxide-semiconductor technology and beyond

In this paper, an alternative approach for the extraction of effective chan nel length, L-eff, using a modified capacitance-voltage (C-V) method [the c apacitance-ratio (C-R) method], which considers depletion effect compensati on is proposed. In general, we define L-eff = L-mask - DeltaL, where DeltaL is the sum of the polysilicon gate lithography bias and two times the over lap length of the polysilicon gate and source/drain (S/D) extension (DeltaL = L-pb + 2L(ovlap)). Using the modified C-V method, more consistent and re asonable L-eff data can be extracted as compared to those obtained using th e newest current-voltage (I-V) method (shift and ratio method). In using th e proposed C-R method, we can electrically measure the exact L-pb and L-ovl ap numbers that can both be used as process monitor parameters. The within- wafer uniformities of L-eff (or DeltaL), L-pb and L-ovlap have also been ch ecked among devices of various sizes. After the L-eff is extracted, a stabl e S/D resistance R-sd, with V-g independence, is determined and verified us ing the I-V method. The parasitic capacitance C-gd is another extracted par ameter that is as important as R-sd in SPICE modeling for PF complementary metal-oxide-semiconductor (CMOS) applications.