Efficient parallel timing simulation of synchronous models on networks of workstations

In this paper we address the parallel timing simulation of synchronous VLSI designs on a network of workstations (NOWs). We suggest combining cycle ba sed and conventional timing simulation techniques to achieve fast timing si mulation even on NOWs which are typically characterized by low bandwidth an d high communication latency. In particular we execute a timing simulator o n each node of the NOW and use cycle based simulation to produce synchroniz ation information required by the timing simulators. As synchronization inf ormation is generated exclusively by the cycle based simulator there is no need for any communication between the timing simulators. To verify the fea sibility and performance of our approach we simulated several circuits usin g our approach. The results show that a significant speedup can be achieved even for very small circuits. (C) 2001 Elsevier Science BY. All rights res erved.