A yet unheralded alternative for future lithography, step-and-flash imprint
lithography, appears to be an inexpensive method for pattern generation ca
pable of sub-100nm resolution on silicon wafers. Researchers at the Univers
ity of Texas have been analyzing various process options on a too[ in place
there and have shown that this process has several advantages over compara
ble compression imprinting techniques for applications that require precisi
on layer-to-layer alignment error measurement. It is capable of high-resolu
tion patterning at room temperature with 2-3 pounds applied pressure. The p
rocess uses chemicals that are commercially available for sub-100nm pattern
s. Development work has been so promising that commercialization is under w
ay.