A novel experimental technique: combined gated-diode method for extractinglateral distribution of interface traps in SOI NMOSFETs

A novel method namely combined gated-diode technique for extracting lateral spatial distribution of interface traps induced by the electrically stress ing is presented in this paper. This technique is based on the measurement of recombination-generation current characteristics via the modulation of t he drain bias voltage of the forward gated-diode. The extracted results on the interface trap profile demonstrate that the induced interface trap dens ity gradually decreases from the drain edge to channel region and shows the highest value near the drain edge. (C) 2001 Elsevier Science Ltd. All righ ts reserved.