ILP-based instruction scheduling for IA-64

The IA-64 architecture has been designed as a synthesis of VLIW and supersc alar design principles. It incorporates typical functionality known from em bedded processors as multiply/accumulate units and SIMD operations for 3D g raphics operations. In this paper we present an ILP formulation for the pro blem of instruction scheduling for IA-64. In order to obtain a feasible sch edule it is necessary to model the data dependences, resource constraints a s well as additional encoding restrictions - the bundling mechanism. These different aspects represent subproblems that axe closely coupled which give s the motivation for a modeling based on integer linear programming. The pr esented approach is divided into two phases which allows us to compute most ly optimal solutions with acceptable computation time.