Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors

Implementation complexity is playing an increasing important role in the de velopment of high-speed microprocessors, in terms of limitations to the act ual cycle time. It is useful for the CPU architecture designer to have an a ssessment of the achievable cycle time when making architecture design deci sions. Formal models exist that allow the designer to have an accurate esti mation of the best possible delay of logic units before doing circuit and l ayout design. The combination of such modeling techniques together with ins truction-level cycle-accurate simulation of the CPU architecture can be a p owerful tool for the development of fast processors. (C) 2001 Elsevier Scie nce B.V. All rights reserved.