Novel serial-parallel multipliers

New designs of serial-parallel multipliers based on the modified Booth and multi-bit recoding algorithms are introduced. Using recoding for the parall el operand, two proposed systolic multipliers have been introduced to build structures having n/2 and n/3 cells. The proposed serial-parallel multipli ers are compared with other structures on the basis of multiplication time, area, and complexity. By using multi-bit overlapped recoding of the multip lier operand, the multiplier operates at twice the speed or the existing de signs and has a much lower AT(2) complexity.